This invention relates to integrated circuit failure analysis, and more particularly, to methods and apparatus for marking faults on semiconductor wafers with lasers to facilitate failure analysis.
Faults are often detected when debugging new integrated circuit designs. Typically, electrical testing is performed on a wafer of integrated circuits to identify faults. To investigate the nature of a suspected fault once it has been identified, it is often desirable to cleave and polish a piece of the wafer in the vicinity of the fault. The piece of polished wafer can then be examined under a scanning electron microscope. Analyzing manufacturing faults in this way allows the sources of faults to be eliminated during manufacturing.
The locations of faults on a wafer must be precisely marked before cleaving and polishing. This is generally accomplished using labor-intensive manual marking procedures. With one known approach, a technician consults a computer-aided-design (CAD) view of the integrated circuit design that is displayed on a computer screen by a CAD program. The technician attempts to navigate to the fault by manually counting visually-recognizable features on the screen. Once the fault has been found, the technician places a cursor at the fault location using the CAD program. The technician then obtains the x-y position of the fault from the x-y position information for the cursor that is displayed by the CAD program.
Having manually identified the x-y position of the defect on the wafer, the technician places the wafer in a laser-equipped probe station. The technician then attempts to manually align the wafer in x, y, and θ to achieve vertical, horizontal, and angular alignment. After aligning the wafer in the vicinity of the defect, the technician can manually step the probe station stage by appropriate horizontal and vertical offset distances to reach marking locations that surround the fault. It is generally necessary to manually realign the wafer in the vicinity of each fault selected for marking.
Conventional marking arrangements such as these are labor intensive and prone to error. It may take hours to mark a single wafer, particularly when the defects are hard to locate in the CAD file or when many manual alignments are required at the probe station. Moreover, the process is dependent on the skills of the technician, which makes it difficult to control the accuracy of the process.